PUBLICATIONS (1995 – Oct. 2021)

Conference Paper (121 papers)

2021

  1. Wei Chang, Yi-Jie Chao, Chrong Jung Lin and Ya-Chin King*, “Physical Unclonable Function by Random Plasma Charging Event in FinFET CMOS Processes,” in 2021 International Electron Devices & Materials Symposium (IEDMS), Tainan, Nov. 2021.
  2. Chia-Ru Lu, Chien-Ping Wang, Jiaw-Ren Shih, Chrong Jung Lin, and Ya-Chin King*, “On-Wafer DUV Detector Through Metal Sensing Pad by 28nm CMOS Technologies,” in 2021 International Electron Devices & Materials Symposium (IEDMS), Tainan, Nov. 2021.
  3. Wei-Cheng Zhuang, Wei-Hwa Lin, Chrong-Jung Lin and Ya-Chin King*, “FinFET-based P-channel Logic Compatible Differential Floating Gate Memory Cells by Cross-coupled Structure,” in 2021 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2021.
  4. Yao-Hung Huang, Chrong Jung Lin and Ya-Chin King*, “Operation Optimization of Logic Compatible 2T RRAM Array by High-κ Metal Gate CMOS Logic Technologies” in 2021 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2021.
  5. Chien-Ping Wang, Burn Jeng Lin, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*, “On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems,” in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2021.
  6. Che-Wei Chu, Chrong Jung Lin, Ya-Chin King* and Wei-Hua Chen, “A Twin Bit AND-Type Multiple-Time-Programming Memory Cell by Nano-scaled High–k Metal Gate Process,” in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2021.

2020

  1. Wei-Cheng Zhuang, Ching-Ting Chien, Chrong Jung Lin and Ya-Chin King*, “Pulse Clamping for Threshold Voltage Control in Embedded Non-volatile Multiple-Level Memory Cell,” in 2020 International Electron Devices & Materials Symposium (IEDMS), Taoyuan, Oct. 2020.
  2. Chih-An Yang, Shi Jiun Wang, Burn Jeng Lin, Chrong Jung Lin and Ya-Chin King*, “On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.
  3. Chi Su, Yi-Jie Chao, Chrong-Jung Lin and Ya-Chin King*, “On-Wafer Recorders for Assessing Wide Range Plasma Induced Charging Effect in FinFET Processes,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.
  4. Chun-Yu Chuang, Chrong-Jung Lin and Ya-Chin King*, “Sidewall Erased Multiple-Time Programmable Memory Cells in FinFET Technologies,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.
  5. Chien-Ping Wang, Ying-Chun Shen, Kun-Lin Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Jiaw-Ren Shih, Chrong Jung Lin and Ya-Chin King*, “Hair-Like Nanostructure Based Ion Detector by 16nm FinFET Technology,” in 2020 IEEE Symposia on VLSI Technology and Circuits (VLSI), Honolulu, HI, June 2020.
  6. Cheng-Jun Lin, Chrong-Jung Lin and Ya-Chin King*, “3D Stackable Via RRAM Cells by Cu BEOL Process in FinFET CMOS Technologies,” in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Aug. 2020.
  7. Fu-Cheng Chang, Yao-Hung Huang, Chrong-Jung Lin and Ya-Chin King*, “A Study of Read Variability in Backfill Contact Random Access Memory,” in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Aug. 2020.

2019

  1. Chieh Lee, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*,“Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks,” in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2019.
  2. Chi Su*, Yi-Pei Tsai, Chrong Jung Lin and Ya-Chin King “Plasma Induced Damage on Inter-Metal Dielectric in Nano-meter FinFET Processes,” in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019.
  3. Yu-Fan Chiang, Che-Wei Chu*, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King “Cross-Coupled Differential Multiple-Time-Programming Memory Cells by CMOS FinFET Technologies,” in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019
  4. Ching-Ting Chien, Chun-Yu Chuang*, Chrong Jung Lin and Ya-Chin King, “Multi-level Operations by Self-clamping Programming Scheme on Fine Floating Gate MTP Cells,” in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019
  5. Yun-Feng Kao, Chrong Jung Lin and Ya-Chin King*, “Stochastic Filament Formation on the Cycling Endurance of Backfilled Contact Resistive Random Access Memory Cells,” 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2019.
  6. Chieh Lee, Yu-Ting Hung, Cheng-Jun Lin, Ya-Chin King, and Chrong Jung Lin*, “Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies,” 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2019.

2018

  1. Yi-Pei Tsai, Jiaw-Ren Shih, Ya-Chin King and Chrong Jung Lin*, “7nm FinFET Plasma Charge Recording Device,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.
  2. Peng-Chun Liou, Tsung-Han Lee, Chien-Ping Wang, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King*, “High Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.
  3. Yu-hung Yeh, Ching-Timg Chien*, Chrong Jung Lin and Ya-Chin King, “Embedded Multiple-Time Programmable Memory by BCD Process for High voltage Circuits,” in 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sept. 2018
  4. Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, “A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors,” in 2018 IEEE International Solid – State Circuits Conference – (ISSCC), San Francisco, CA, April 2018, pp. 494-496.
  5. Jen Chieh Kuo, Ya-Chin King* and Chrong-Jung Lin, “Temperature Effect on Operations and Characteristics of p-channel FinFET Dielectric RRAM,” in 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, April 2018, pp. 1-2.
  6. Chih-Yuan Chen, Chrong Jung Lin and Ya-Chin King*, “Temperature and Stress Effect of Random Telegraph Noise in FIND RRAM Arrays,” in 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, April 2018, pp. 1-2.
  7. Zih-Hong Chen, Chien-Ping Wang, Po-Hsiang Huang, Chrong Jung Lin and Ya-Chin King*, “Embedded Tunable Near Infrared Sensor with Programmable Potential Barrier on Nano-meter CMOS Platforms,” in 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Mar. 2018, pp. 274-276.

2017

  1. Wei-Yu Chien, Tai-Min Wang, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, and Ya-Chin King*, “Twin Mode NV Logic Gates for High Speed Computing System on 16nm FINFET CMOS Logic Process,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2017, pp. 12.1.1-12.1.4.
  2. Peng-Chun Liou, Bo-Rong Huang, Chrong-Jung Lin and Ya-Chin King, “Atto-Farad Capacitance Measurement for FinFETs by Vertical Fin Coupling Structure,” in 2017 International Electron Devices & Materials Symposium (IEDMS), Hsinchu, Sep. 2017.
  3. Zih-Hong Chen, Yu-hung Yeh, Po-Ruei Cheng, Chrong Jung Lin, Ya-Chin King, “An Investigation of Light Triggering Effect on the Programming of Gate-less Anti-Fuse Cells,” in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sept. 2017
  4. Yi-Hong Shih, Meng-Yin Hsu, Chrong Jung Lin and Ya-Chin King, “Twin-bit Via RRAM in 16nm FinFET Logic Technologies,” in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sept. 2017
  5. Wei-Ting Hsieh, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin and Ya-Chin King, “Differential Contact RRAM Pair for Advanced CMOS Logic NVM applications,” in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sep. 2017
  6. Tai-Min Wang, Wei-Yu Chien, Chia-LingHsu, Yue-Der Chih, Chrong Jung Lin, and Ya-Chin King*, “P-channel Differential Multiple-Time Programmable Memory Cells by Laterally Coupled Floating Metal Gate FinFETs,” in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sep. 2017
  7. Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Mon-Shu Ho and Meng-Fan Chang*, “Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications,” in 2017 Symposium on VLSI Circuits, Kyoto (VLSI), 2017, pp. C164-C165.
  8. Yu-Hung Yeh, Sheng-Hung Shih, Jen-Chien Fu, Chrong-Jung Lin and Ya-Chin King*, “An Investigation of Program Disturb Characteristics and Data Pattern Effect in 128G 3D NAND Flash Memories,” in 2017 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, 23 Apr. 2017
  9. Yi-Hung Chang, Po Shao Yeh, Yue-Der Chih, Jonathan Chang, Ya-Chin King and Chrong Jung Lin*, “3D Time-Contingent Physical Unclonable Function Array on 16nm FinFET Dielectric RRAM,” in 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Mar. 2017.
  10. Ting-Huan Hsieh, Yi-Pei Tsai, Chrong Jung Lin and Ya-Chin King*, “Charge Splitting In-situ Recorder (CSIR) for Monitoring Plasma Damage in FinFET BEOL Processes,” in 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Mar. 2017.

2016

  1. Jo En Yuan, Jen Chieh Kuo, Yu-Zheng Chen, Chrong Jung Lin, Ya-Chin King , “An Investigation of P-channel One-Time-Programming Cells by High-κ Metal Gate CMOS Logic Process” in 2016 International Electron Devices & Materials Symposium (IEDMS), Nov. 2016.
  2. Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Ya-Chin King, Chrong Jung Lin, Yongpan Liu, Huazhong Yang, Pedram Khalili, Kang-Lung Wang, and Meng-Fan Chang*, “A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era,” 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 16.3.1-16.3.4.
  3. Chu-Feng Liao, Meng-Yin Hsu, Yu-Der Chih, Ya-Chin King*, and Chrong Jung Lin, “Zero Static-Power 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process,” 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2016.
  4. Chia-Ling Hsu, Chu-Feng Liao, Wei-Yu Chien, Yue-Der Chih, Chrong Jung Lin, and Ya-Chin King, “Differential Multiple-Time-Programming Memory Cells by Laterally Coupled Floating Metal Gate FinFETs,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 29 Sep. 2016.
  5. Bo-Rong Huang, Fan-Hsuan Meng, Ya-Chin King and Chrong Jung Lin, “An Investigation of the Parasitic RC Effects in Nano-scaled FinFETs and Its Impact on SRAM Cells,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 29 Sep. 2016.
  6. Yun Feng Kao, Wei Ting Hsieh, Chun Che Chen, Ya-Chin King, and Chrong Jung Lin, “Statistical Analysis of the Correlations between Cell Performance and its Initial States in CRRAM Cells,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 27 Sep. 2016.
  7. Hsien Hao Chen, Sheng-Hung Shih, Ya-Chin King, and Chrong Jung Lin, “Design and characterization of Logic Compatable Drain Extended FinFETs for Embedded High-Voltage Circuits,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Sep. 2016.
  8. Meng-Yin Hsu, Yu-Der Chih, Ya-Chin King, and Chrong Jung Lin, “Gate Contact RRAM in Nano-scaled FinFET Logic Technologies,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 27 Sep. 2016.
  9. Mingte Lin, Chihching Yang, Hung-Yu Chen, Alex Juan, K. C. Su and Ya-Chin King “Evaluation of inter and intra level TDDB of Cu/Low-k interconnect for high voltage application,” 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, 2016, pp. DI-6-1-DI-6-4.
  10. Hung-Yu Chen, Hsien-Hao Chen, Yun-Feng Kao, Ping-Yu Chen, Ya-Chin King, Chrong Jung Lin*, “A new manufacturing method of CMOS logic compatible 1T-CRRAM,” 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2016, pp. 1-2.
  11. Po-Ruei Cheng, Chih-Sung Yang, Meng-Yin Hsu, Chrong Jung Lin, Ya-Chin King* , “Variable-length gateless transistor for analog one-time-programmable memory applications,” 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2016, pp. 1-2.

2015

  1. Chun-Hsiung Wu, Yi-Pei Tsai, Chrong Jung Lin, Ya-Chin King*, “Mapping of Wafer-Level Plasma Induced Charge Contour by Novel On-chip In-Situ Recorders in Advance FinFET Technologies,” in 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., 7-9 Dec. 2015.
  2. Hsin Wei Pan, Kai Ping Huang, Shih Yu Chen, Ping Chun Peng, Zhi Sung Yang, Cheng-Hsiung Kuo, Yue-Der Chih, Ya-Chin King and Chrong Jung Lin*, ” 1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process,” in 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., 7-9 Dec. 2015.
  3. Ping Chun Peng, Yu-Zheng Chen, Hsin Wei Pan, Woan Yun Hsiao, Kuang-Hsin Chen, Yu-Hsuan Kuo, Ching-Pin Lin, Bor-Zen Tien, Tzong-Sheng Chang, Ya-Chin King*, and Chrong Jung Lin, “A New High Density FinFET OTP Technology,” in 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, 30 Sep. 2015.
  4. Po-Yen Lin, Yu-Lun Chiu, Fan-Hsuan Meng, Kuang-Hsin Chen, Serena Hao, Bor-Zen Tien, Tzong-Sheng Chang, Chrong Jung Lin and Ya-Chin King*, “Effect of 3D Current Distribution on Characterizing Parasitic Resistance of FinFETs,” in 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, 27 Sep. 2015.
  5. Yu-Wen Chung; Wen Chao Shen; Ping-Yu Chen; Zih-Song Wang; Huei-Haurng Chen; Ming-Jinn Tsai; Ya-Chin King; Chrong Jung Lin*, “A new ultra high density 1F1R MLC flash contact RRAM,” in VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on., pp.1-2, 27-29 April 2015.
  6. Liang-Shun Chang; Yi-Che Yen; Kuei-Hung Shen; Ming-Jinn Tsai; Chrong Jung Lin; Ya-Chin King*, “Multi-channel magnetic transmission interface for 3D contactless connection,” in VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on , pp.1-2, 27-29 April 2015.

2014

  1. Yung-Wen Chin; Shu-En Chen; Min-Che Hsieh; Tzong-Sheng Chang; Chrong Jung Lin; Ya-Chin King*, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process,” in 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014.
  2. Yuh-Te Sung; Po-Yen Lin; Jim Chen; Tzong-Sheng Chang; Ya-Chin King; Chrong Jung Lin*, “A new saw-like self-recovery of interface states in nitride-based memory cell,” in 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2014.
  3. Sheng-Yen Chien; Po Yen Lin; Hung-Yu Chen; Chrong Jung Lin; Ya-Chin King*, “Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs,” in VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program – 2014 International Symposium on , pp.1-2, 28-30 April 2014.
  4. Woan Yun Hsiao; Chin Yu Mei; Wen Chao Shen; Tzong Sheng Chang; Yue Der Chih; Ya-Chin King; Chrong Jung Lin*, “A high density Twin-Gate OTP cell in pure 28nm CMOS process,” in VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program – 2014 International Symposium on , pp.1-2, 28-30 April 2014.

2013

  1. Min-Che Hsieh, Yu-Cheng Liao, Yung-Wen Chin, Chen-Hsin Lien, Tzong-Sheng Chang, Yue-Der Chih, Sreedhar Natarajan, Ming-Jinn Tsai, Ya-Chin King, and Chrong Jung Lin*, “Ultra High Density 3D Via RRAM in Pure 28nm CMOS Process”, International Electron Devices Meeting (IEDM), New York, 2013.
  2. Ching-Hua Wang, Kun-Yu Dai, Kuei-Hung Shen,Yung-Hung Wang, and Ming-Jinn Tsai, Chrong Jung Lin and Ya-Chin King*, “Magnetic Wireless Interlayer Transmission through Perpendicular MTJ for 3D-IC Applications”, International Electron Devices Meeting (IEDM), New York, 2013.

2012

  1. Wen Chao Shen , Chin Yu Mei, Y. -D. Chih, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, “High-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process,” 2012 International Electron Devices Meeting (IEDM), San Francisco, Dec. 2012.
  2. Wang, K. Y. Tai1, L. C. Wang, C. Lin, C. H. Huang, C. J. Lin, and Y. C. King, “Super Junction Power MOSFET by Multi-step Trench Process,” 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012.
  3. Tsao-Hsin Yang, Una Liauh, Y.-D. Chih, Chrong Jung Lin, Ya-Chin King, “Single Contact RRAM in Pure 65nm CMOS Logic Process,” 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012.
  4. Chang, C. W. CW, C. C. Kuo, S. J. Shen, S. M. Yang, K. F. Lin, Y. C. King, C. J. Lin, and Y. D. Chih, “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time” 2012 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012.

2011

  1. Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chrong Jung Lin, Hung-Jen Liao, Yu-Der Chih, and Hiroyuki Yamauchi, “An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory”, 2011 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2011.

2010

  1. Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, and Chrong Jung Lin, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, and Ming-Jinn Tsai, “Three-Dimensional 4F(2) ReRAM Cell with CMOS Logic Compatible Process”, 2010 International Electron Devices Meeting (IEDM), Dec. 2010.
  2. Yuan Heng Tseng;Wen Chao Shen;Chia-En Huang;C. -H. Kuo;Y. -D. Chih;Chrong Jung Lin;Ya-Chin King, “Electron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis”, 2010 International Electron Devices Meeting (IEDM), Dec. 2010.

2009

  1. Te-Yu Lee, Chih-Chieh Chiu, Chrong Jung Lin and Ya-Chin King, “High-Uniformity 2T1C AMOLED Panels by Using a New Built-In Trimming Method”, 2009 International Symp. of the Society for Information Display (SID).
  2. Yuan Heng Tseng, Chia-En Huang, C. -H. Kuo, Y. -D. Chih, Chrong Jung Lin, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, 2009 IEEE International Electron Devices Meeting (IEDM), 2009.
  3. Tzu-Hsuan Hsu, Hang-Ting Lue, Sheng-Chih Lai, Ya-Chin King, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, “Reliability of planar and FinFET SONOS devices for NAND flash applications – Field enhancement vs. barrier engineering”, VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, 2009, pp. 154-155.

2008

  1. Dai, C. J. LinY. C. Kinget al., “Low voltage transient voltage suppressor with v-groove structurec,” 2008 IEEE International Reliability Physics Symposium Proceedings – 46th Annual, International Reliability Physics Symposium, pp. 278-282, New York: IEEE, Electron Devices Soc & Reliability Group, 2008.
  2. Hsu, H. T. Lue, W. C. Peng, C. H. Tsai, Y. C. King, S. Y. Wang, M. T. Wu, S. P. Hong, J. Y. Hsieh, L. W. Yang, N. T. Lian, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, A study of sub-40nm FinFET BE-SONOS NAND flash, New York: IEEE, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings
  3. Hsu, H. T. Lue, W. C. Peng, Y. C. King, C. W. Wu, S. Y. Wang, M. T. Wu, S. P. Hong, J. Y. Hsieh, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, High performance and scalable FinFET BE-SONOS device for NAND Flash memory application, New York: IEEE, 2008 International Symposium on Vlsi Technology, Systems and Applications

2007

  1. Tsai, H. M. Chen, H. Y. Chiu, H. S. Shih, H. C. Lai, Y. C. King, C. J. Lin, “45nm gateless anti-fuse cell with CMOS fully compatible process,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 95-98, New York: IEEE, 2007.
  2. Liang, S. I. Hsieh, H. T. Chen, C. J. Lin, Y. C. King, “Degradation dependent on channel width in sequential lateral solidified poly-Si thin film transistors,” 2007 IEEE International Reliability Physics Symposium Proceedings – 45th Annual, International Reliability Physics Symposium, pp. 682-683, New York: IEEE, 2007.
  3. Huang, H. M. Chen, H. C. Lai, Y. J. Chen, Y. C. King, C. J. Lin, “A new self-aligned nitride MTP cell with 45nm CMOS fully compatible process,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 91-94, New York: IEEE, 2007.
  4. Huang, H. M. Chen, M. B. Chen, Y. C. King, C. J. Lin, A new CMOS logic anti-fuse cell with programmable contact, New York: IEEE, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, New York: IEEE, 2007.
  5. Hisu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, L. W. Yang, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, “A high-speed BE-SONOS NAND Flash utilizing the field-enhancement effect of FinFET,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 913-916, New York: IEEE, 2007.
  6. Dai, H. N. Wang, M. T. Chiang, C. J. Lin, Y. C. King, “Leakage suppression of low voltage transient voltage suppressor,” 2007 IEEE International Reliability Physics Symposium Proceedings – 45th Annual, International Reliability Physics Symposium, pp. 592-593, New York: IEEE, 2007.
  7. Cho, C. T. Peng, W. J. Chiang, C. J. Lin, C. W. Chao, K. C. Lin, Y. C. King, C. S. Weng, F. Y. Gan, Integrated ambient light sensor in LTPS LCD panel with silicon nanocrystals photosensor, Minato-Ku: Inst Image Information & Television Engineers, Idw ’07: Proceedings of the 14th International Display Workshops, Vols 1-3, 2007.
  8. Chiang, C. Y. Chen, C. J. Lin, Y. C. King, A. T. Cho, C. T. Peng, C. W. Chao, K. C. Lin, F. Y. Gan, “Late-news poster: Silicon nanocrystals photo sensor integrated on low-temperature polycrystalline-silicon panels,” 2007 Sid International Symposium, Digest of Technical Papers, Vol Xxxviii, Books I and Ii, Sid International Symposium Digest of Technical Papers, pp. 294-297, Playa Del Rey: Soc Information Display, 2007 Sid International Symposium, Digest of Technical Papers, Vol Xxxviii, Books I and Ii

2006

  1. Chiang, H. C. Chen and Y. C. King“Photodiode Model for CMOS Image Sensor SPICE Simulation”, International Conference on Solid State Devices and Materials, Tokyo, Japan, September 2006

2005

  1. Chen HT, Hsieh SI, Chen YC, Tsai PH, Chen CL, Huang CJ, Lin JX, Chang CJ, King YC. “Novel flash memory structure using sequential lateral solidified low temperature poly-Si technology”. IDW/AD’05 – Proceedings of the 12th International Display Workshops in Conjunction with Asia Display 2005; 2005; Takamatsu, Japan
  2. Wu M-Y, Feng S-C, King Y-C. “A novel single poly-silicon EEROM using trench floating gate”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan
  3. Hu L-C, Kang A-C, Wu TI, Chen E, Shih JR, Chin HW, Lin Y-F, Wu K, King Y-C. “A voltage acceleration lifetime model to predict post-cycling LTDR characteristics of split-gate flash memories”. IEEE International Reliability Physics Symposium Proceedings; 2005; San Jose, CA, United States
  4. Chang YW, Chang HW, Lu TC, King Y, Ting W, Ku J, Lu CY. “A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance”. IEEE International Conference on Microelectronic Test Structures; 2005; Leuven, Belgium.
  5. Lee K-H, Wang S-C, King Y-C. “Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan
  6. Lai C-H, King Y-C, Huang S-Y. “A 1.2V 0.25-μm clock output pixel sensor with wide dynamic range”. Proceedings of SPIE – The International Society for Optical Engineering; 2005; San Jose, CA, United States
  7. Ssu-I Hsieh and Ya-Chin King, “Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric”, Proceeding for the 2005 International Conference on Solid State Devices and Materials, Tokyo, Japan
  8. Cheng-Hsiao, Liang-Wei Lai, and Ya-Chin King,“ A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT”,Proceeding for the 2005 International Conference on Solid State Devices and Materials, pp. 940-941 Tokyo, Japan
  9. Wei-Cheng Lin and Ya-Chin King,“Reliability Evaluation of 5.2GHz CMOS Receiver”, European Microwave Conference, France, October 2005

2004

  1. Lin W-C, Du L-J, King Y-C. “Reliability evaluation and comparison of class-E and class-A power amplifiers with 0.18 μm CMOS technology”. Annual Proceedings – Reliability Physics (Symposium); 2004; Phoenix, AZ., United States.
  2. Lin W-C, Du L-J, King Y-C. “Reliability evaluation of Gilbert Cell mixer based on a hot-carrier stressed device degradation model”. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers; 2004; Fort Worth, TX, United States.
  3. Lin C-I, Lai C-H, King Y-C. “A four transistor CMOS active pixel sensor with high dynamic range operation”. Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits; 2004; Fukuoka, Japan.
  4. Hu L-C, Kang A-C, Liu IT, Lin Y-F, Wu K, King Y-C. “Statistical modeling for post-cycling data retention of split-gate flash memories”. Annual Proceedings – Reliability Physics (Symposium); 2004; Phoenix, AZ., United States.
  5. Kung-Hong Lee, Meng-Yi Wu, Sen-Hue Dai and Ya-Chin King, “CMOS-process-based ultra high density Flash Memory Cell and Array Architecture”, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004
  6. Cheng-Hsiao Lai, Yueh-Ping Yu, Ya-Chin King, “A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors”, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004
  7. Meng-yi Wu, Kung-Hong Lee1, Sen-Hue Dai1, Shu-Fen Hu, Ya-Chin King, “Low Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming.”, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004

2003

  1. Shih-Fang, Chen Ying-Jie Juang, Shi-Yu Huang, Ya-Chin King, “Logarithmic CMOS Image Sensor Through Multi-Resolution Analog-To-Digital Conversion”, International Symposium on VLSI Technology, system and Applications (Hsinchu, Taiwan) , Sept. 2003
  2. Lai, H.C.; Zous, N.K.; Tsai, W.J.; Lu, T.C.; Tahui Wang; King, Y.C.; Pan, S.“Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFET’s ”, International Conference on Microelectronic Test Structures, March 17 – 20, 2003
  3. Lin W-C, Du L-J, King Y-C. “Reliability evaluation of voltage controlled oscillators based on a device degradation sub-circuit model”. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers; 2003; Philadelphia, PA, United States
  4. Chang S, Yang E, Chen T, Huang L, Hsu B, Sung D, Duh J-C, Hung C-W, Huang V, King Y-Cand others. “New Buried Bit-line NAND (BiNAND) Flash Memory for Data Storage”. Digest of Technical Papers – Symposium on VLSI Technology; 2003; Kyoto, Japan.
  5. Lee K-H, King Y-C. “New Single-poly EEPROM with Cell Size down to 8F2 for High Density Embedded Nonvolatile Memory Applications”. Digest of Technical Papers – Symposium on VLSI Technology; 2003; Kyoto, Japan
  6. Po-Hao Huang, Ya-Chin King, “Optimization of The Ultra-Low Dark Current CMOS Image Sensor Cell Using n+ Ring Reset”, International Conference on Solid State Devices and Materials, Tokyo, September 2003
  7. Wang T, Pan S, Lai HC, Zous NK, Tsai WJ, Lu TC, King YC. “Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFET’s”. IEEE International Conference on Microelectronic Test Structures; 2003.

2002

  1. Liang-Wei Lai, Ya-Chin King,“A Novel Logarithmic Response CMOS Image Sensor With High Output Voltage Swing and In-pixel Fixed Pattern Noise Reduction”, The Third IEEE Asia Pacific Conference on ASICs, August 2002
  2. Hsien-Chun Chang, Ya-Chin King, “Tunable Injection Current Compensation Architecture for High Fill-factor Self-buffered Active Pixel Sensor”, The Third IEEE Asia Pacific Conference on ASICs, 6-8 August 2002
  3. Sing –Rong Lee, Ya-Chin King, “ A New Sampling Scheme for High Sensitive, Extended Dynamic Range CMOS Imaging Pixel Sensors”, 2002 International Conference on Solid State Devices and Materials, Tokyo, September 2002

2001

  1. She M, King YC, King TJ, Hu C. “Modeling and design study of nanocrystal memory devices”. Annual Device Research Conference Digest; 2001; Notre Dame, IN. p 139.
  2. Lai CH, Hu LC, Lee HM, Do LJ, King YC. “New stack gate insulator structure reduce FIBL effect obviously”. International Symposium on VLSI Technology, Systems, and Applications, Proceedings; 2001; Hsinchu. p 216.
  3. Hsiu-Yu Cheng, Hsien-Chun Chang, Shing-Rung Li, Liang-Wei Lai, Shuh-Sen Lin and Ya-Chin King, “A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-μm CMOS Imagers”, 2001 International Conference on Solid State Devices and Materials, Tokyo, September 2001, pp.286-287

2000

  1. Amy H.-F. Chou; Yu-Yuan Yao,; Wei-Zhe Wong; Evans Ching-Song Yang, Yen-Sen Wang; Ya-Chin King; Charles Hsu.”New Coupling Ratio Extraction Method for Split Gate Flash Memory.”, Non-volatile Workshop, Montery, U.S.A., 2000, pp. 84-85

1999

  1. Yang K, King Y-C, Hu C. “Quantum effect in oxide thickness determination from capacitance measurement”. Digest of Technical Papers – Symposium on VLSI Technology; 1999; Kyoto, Japan.
  2. Amy H.-F. Chou; Evans Ching-Song Yang; Wei-Zhe Wong; Ya-Chin King; Charles Hsu. ” A New-bitline-controlled Self-convergent Multi-level AND type Flash Memory” International Conference on Solid State Device and Materials, pp. 536-537, Tokyo, Japan, 1999.
  3. Amy H.-F. Chou; Wei-Zhe Wong; Evans Ching-Song Yang, Yu-Yuan Yao; Yen-Sen Wang; Ya-Chin King; Charles Hsu., “Comprehensive study of a new self-convergent programming scheme for split gate flash memory.” International Conference on Solid State Device and Materials, pp. 540-541, Tokyo, Japan, 1999.

1998

  1. King Y-C, Kuo C, King T-J, Hu C. “Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation”. Technical Digest – International Electron Devices Meeting; 1998; San Francisco, CA, USA.
  2. King Y-C, King T-J, Hu C. “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”. Technical Digest – International Electron Devices Meeting; 1998; San Francisco, CA, USA.

1997

  1. King Y-C, Fujioka H, Kamohara S, Lee W-C, Hu C. “AC charge centroid model for quantization of inversion layer in n-MOSFET”. International Symposium on VLSI Technology, Systems, and Applications, Proceedings; 1997; Taipei, Taiwan
  2. Shiro Kamohara; Ya-Chin King; Kai Chen; Dongun Park; Hu C.. “MOSFET carrier mobility model based on the density-of-state at the DC-centroid in the quantized inversion layer.”, International Conference on VLSI and CAD, Seoul, South Korea, 1997. p.171.

1996

  1. Fujioka H, Wann HJ, Park DG, King YC, Chyan YF, Oshima M, Hu C. “Tunneling current through MIS structures with ultra-thin insulators”. Materials Research Society Symposium – Proceedings; 1996; San Francisco, CA, USA

1995

  1. Zhang G, King Y, Eltoukhy S, Hamdy E, Jing T, Yu P, Hu C. “On-state reliability of amorphous silicon antifuses”. Technical Digest – International Electron Devices Meeting; 1995
  2. Yu B, King Y-C, Pohlman J, Hu C. “Punchthrough transient voltage suppressor for EOS/ESD protection of low-voltage IC’s”. Electrical Overstress/Electrostatic Discharge Symposium Proceedings; 1995; Phoenix, AZ, USA.