林崇榮 CHRONG JUNG LIN

現職

國立清華大學電機系暨電子工程研究所教授

電機系微電子實驗室負責人

 

電機系先進快閃記憶體中心副主任

 

國際電機電子工程學會資深會員

 

世界先進積體電路公司(VIS)協理-借調

 

研究方向

 

快閃記憶體,半導體記憶體技術、積體電路元件、功率電晶體

 

學歷

 

Ph.D 12/1996           國立清華大學電機系

 

M.S. 06/1992           國立清華大學電機系

 

經歷

現職                               國立清華大學電機系教授

2015/12 ~              世界先進積體電路公司(VIS)協理-借調

1996/04 ~ 2005/07         台灣積體電路公司(TSMC)研發經理

專業領域貢獻

1.      Institute of Electrical and Electronics Engineers (IEEE), IEEE Senior Member

2.      Program Committee Member of Int’l Symp. on VLSI Technology, Systems and Applications (VLSI-TSA)

3.      Program Committee Member of IEEE International Electron Devices Meeting (IEDM)

4.    International Advisory Board Member of International Conference on Modern Materials and Technologies (CIMTEC).

5.      Session Chair of VLSI Tech, Systems, and Application (VLSI-TSA)

6.      Session Chair of IEEE International Electron Devices Meeting (IEDM)

7.      Coordinator of RRAM Technology Cooperation Project (Technion - Israel Institute of Technology)

8.      2010 Best Paper Award of International Society for Information Display (SID) Conference

9.      學校科技權益委員會委員

10.      STPI 國家實驗院專利分析之專家委員

11.  經濟部工業局產業科專之審查委員

12.  技審會主導開發計畫之訪查委員

13.  工研院創業育成廠商進駐審查委員

14.  資策會(MIC)台灣產業科技前瞻研究計畫(2020/2025計畫)審查委員

 林崇榮 CHRONG JUNG LIN

CURRENT POSITIONS

Professor, Department of Electrical Engineering and Institute of Electronics Engineering

Leader of Microelectronics Laboratory, Department of Electrical Engineering

Institute of Electrical and Electronics Engineers (IEEE), Senior Member

Deputy Director of Center of Advanced Flash Memory (CAFM)

Program Committee Member of Int’l Symp. on VLSI Technology, Systems and Applications (VLSI-TSA)

Program Committee Member of IEEE International Electron Devices Meeting (IEDM)

EDUCATION

Ph.D.       12/1996           Department of Electrical Engineering, National Tsing Hua University (NTHU)

EXPERIENCE

Now                               Professor, Department of Electrical Engineering and Institute of Electronics Engineering, National Tsing Hua University

2015/12~                        Assistant Vice President, Vanguard International Semiconductor Corporation (VIS)

1996/04 ~ 2005/07         Program Manager, R&D, Taiwan Semiconductor Manufacturing Company (TSMC)

RESEARCH ORIENTATION

Flash Memory, Semiconductor Memory Technology, VLSI Device, Power IC

Contribution in Expertise

1.      Institute of Electrical and Electronics Engineers (IEEE), IEEE Senior Member

2.      Program Committee Member of Int’l Symp. on VLSI Technology, Systems and Applications (VLSI-TSA)

3.      Program Committee Member of IEEE International Electron Devices Meeting (IEDM)

4.      Session Chair of VLSI Tech, Systems, and Application (VLSI-TSA)

5.      Seesion Chair of IEEE International Electron Devices Meeting (IEDM)

6.      Coordinator of RRAM Technology Cooperation Project (Technion - Israel Institute of Technology)

7.      2010 Best Paper Award of International Society for Information Display (SID) Conference

8.      學校科技權益委員會委員

9.      STPI 國家實驗院專利分析之專家委員

10.  經濟部工業局產業科專之審查委員

11.  技審會主導開發計畫之訪查委員

12.  工研院創業育成廠商進駐審查委員

13.  資策會(MIC)台灣產業科技前瞻研究計畫(2020/2025計畫)審查委員

Biography

  Prof. CHRONG JUNG LIN was born in Taipei, Taiwan in 1969 and received the B.S., M.S., and Ph.D. degrees from the National Tsing-Hua University (NTHU), Hsinchu, Taiwan, R.O.C., in 1991, 1992, and 1996. He obtained his Electrical Engineering Ph.D. degree in 1996 by the study of tunneling enhancement effect of silicon nano-crystal in Flash memory application. From 1996, he had started to work in the Research and Development Division of Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan. His work was mainly focused on the development of advanced 0.13um CMOS logic technology and embedded flash memory on CMOS logic platform. From 1999 to 2003, a 0.25um embedded flash memory for automotive Micro Control Unit (MCU) application has been developed by the research team under his lead. It is the first work of 0.25um automotive split gate Flash chip in the worldwide. Between 2003 and 2005, he had moved on to be in charge of the technology development of 0.18um commercial and automotive embedded flash memory, then successfully to develop 0.18um embedded Flash MCU and Bluetooth chips with the team he lead. During the period of working in R&D, TSMC, he has granted 57 US patents and 43 Taiwan patents in the research field. From 1999, He was awarded every year by TSMC’s top management due to his productive innovation and creativity. Since 2005, he has started to teach in the Institute of Electronics Engineering, the Department of Electrical Engineering of National Tsing Hua University in Taiwan. The orientations of his research include the ReRAM memory, advanced nonvolatile memories, semiconductor power device, and optical sensors in panel applications.

Prof. Lin has been leading the Microelectronics Laboratory and Advanced Flash memory center of National Tsing Hua University from 2005 until now. A lot of novel memory devices and technologies have been innovated and developed by his research team. After promoted to associate professor, between 2008 to Feb. 2013, total 31 journal papers and 9 important conference papers have been published by Prof. Lin; regarding the ReRAM field, he has had 5 important journal papers and 6 conference papers, those are including 4 IEEE IEDM papers and 2 ISSCC papers, two brand new ReRAM technologies and related physics mechanism have been created and presented in the publications. Moreover, his 2010 and 2012 IEDM (IEEE International Electron Devices Meeting) papers were reported on IEEE Spectrum and London’s EE Times for recognizing the advanced ReRAM technology research of Taiwan. Besides, in the research of nonvolatile memory, 15 journal papers including more than 8 new and innovative NVM cells and technologies have been innovated and presented. Additionally, in terms of Semiconductor Power Device and Light Sensor, he has also published 3 and 9 papers in the two fields, respectively. Moreover, one of his SID (International Society for Display Information Conference) conference papers further granted the award of “Best Paper of the Year 2010” in this famous display forum. In the accomplishment of patent innovation, 10 US patents and 11 TW patents have been granted in 2008 to Feb.2013 and a lot of original works and creative technologies are innovated.

Prof. Lin is a Professor of Department of Electrical Engineering and Institute of Electronics Engineering, National Tsing Hua University, he also is an IEEE Senior member and Technical Program Committee Member of International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) and the IEEE International Electron Devices Meeting (IEDM, Memory Technology session).

.

PUBLICATIONS (2008 - 2013)

Journal Paper

J1.       Chang LS, Huang CY, Tseng YH, King YC, Lin CJ*, “Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM,” IEEE Electron Device Letters, vol. 34, no. 1, pp. 12-14, Jan, 2013. (Corresponding Author)

J2.       Wang ZS, Lee YJ, Yang R, Lin YC, Chen HH, Lin CJ*, “A New Recess Method for SA-STI NAND Flash Memory,” IEEE Electron Device Letters, vol. 33, no. 6, pp. 896-898, Jun, 2012. (Corresponding Author)

J3.       Lien CW, Wu HY, Tsai CW, Huang CM, Chih YD, Lee TL, Lin CJ*, “A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process,” IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1899-1905, Jul, 2012. (Corresponding Author)

J4.       Huang CY, Shen WC, Tseng YH, King YC, Lin CJ*, “A Contact-Resistive Random-Access-Memory-Based True Random Number Generator,” IEEE Electron Device Letters, vol. 33, no. 8, pp. 1108-1110, Aug, 2012. (Corresponding Author)

J5.       Huang CC, Huang JKT, Lee CW, Lin CJ*, “A CMOS Active Pixel Sensor With Light Intensity Filtering Characteristics for Image Thresholding Application,” IEEE Sensors Journal, vol. 12, no. 5, pp. 1289-1293, May, 2012. (Corresponding Author)

J6.       Tseng YH, Shen WC, Lin CJ*, “Modeling of Electron Conduction in Contact Resistive Random Access Memory Devices as Random Telegraph Noise,” Journal of Applied Physics (JAP), VOL. 111, NO. 7, April, 2012. (Corresponding Author)

J7.       Yang LY, Hsieh MC, Liu JS, Chin YW, and Lin CJ*, “A Highly Scalable Interface Fuse for Advanced CMOS Logic Technologies,” IEEE Electron Device Letters (EDL), VOL. 33, NO. 2, FEBRUARY 2012 (Corresponding Author) 

J8.       Shen WC, Tseng YH, Chih YD, and Lin CJ*, “Memristor Logic Operation Gate With Share Contact RRAM Cell,” IEEE Electron Device Letters (EDL), VOL. 32, NO. 12, DECEMBER 2011 (Corresponding Author)

J9.       Wu HY, Tsai CW, Lien CW, Chih YD, Lin CJ*, “A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process,” IEEE Electron Device Letters(EDL), vol. 32, no. 10, pp. 1352-1354, Oct, 2011. (Impact factor in top of 10) (Corresponding Author)

J10.   Wang CH, Tsai YH, Lin KC, Chang MF, King YC, Lin CJ*, Sheu SS, Chen YS, Lee HY, Chen FT, and Tsai MJ, “Three-Dimensional 4F2 ReRAM with Vertical BJT Driver by CMOS Logic Compatible Process,” IEEE Transactions on Electron Devices(TED), vol. 58, no. 8, pp. 2466-2472, Aug, 2011. (Impact factor in top of 15) (Corresponding Author) 

J11.   Lee TL, Tsai YH, Lin WJ, Yang HL, Lien CW, Lin CJ*, King YC, “A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation,”  IEEE Electron Devices Letters, vol. 32, Issue:5, Pages: 587-589, May 2011. (Corresponding Author)

J12.   Chen CY, Lin CJ, King YC, “A New Sensing Scheme for Sensitivity Enhancement of Low-Temperature Polycrystalline Silicon Photo detectors”, IEEE Sensors Journal, Volume: 11 Issue: 6 Pages: 1478-1483, Jun 2011.

J13.   Tseng YH, Huang CE, Kuo CH, Chih YD, King YC, Lin CJ*, “A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits”, IEEE Transactions on Electron Devices (TED), vol. 58, no. 1, pp. 53-58, Jan, 2011. (Corresponding Author)

J14.   Liu SE, Yu MJ, Lin CY, Ho GT, Cheng CC, Lai CM, Lin CJ*, King YC, Yeh YH, “Influence of Passivation Layers on Characteristics of a-InGaZnO Thin-Film Transistors”, IEEE Electron Device Letters (EDL), vol. 32, no. 2, pp. 161-163, Feb, 2011.

J15.   Tsai YH, Yang HL, Lin WJ, Lin CJ*, King YC, “A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010. (Corresponding Author) 

J16.   Lee TY, Lin CJ*, King YC, “High-uniformity 2T1C AMOLED panels by a built-in trimming method”, Journal of the Society for Information Display(SID), vol. 18, no. 8, pp. 544-549, Aug, 2010.

J17.   Huang CE, Tseng YH, Kuo CH, Chih YD, King YC, Lin CJ*, “Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 1, 2010. (Corresponding Author) 

J18.   Huang CE, Chen YJ, Hsun OY, Lin CJ*, King YC, “Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications”, Japanese Journal of Applied Physics(JJAP), vol. 49, no. 4, 2010. (Corresponding Author) 

J19.   Dai SH, Peng JJ, Chen CC, Lin CJ, King YC, “Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor”, Japanese Journal of Applied Physics(JJAP), vol. 49, no. 4, 2010.

J20.   Chen CY, Lin CJ, King YC, “Integration of Microcoil Magnetic Manipulation with High-Sensitivity Complementary Metal-Oxide-Semiconductor Photosensor Detection in Bio-Analyses”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010. 

J21.   Tsai YH, Lin KC, Kuo CH, Chih YD, Lin CJ*, King YC, “A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate”, IEEE Electron Device Letters(EDL), vol. 30, no. 10, pp. 1090-1092, Oct, 2009. (Corresponding Author) 

J22.   Tsai YH, Lin KC, Chiu HY, Shih HS, King YC, Lin CJ*, “A study of gateless OTP cell using a 45 nm CMOS compatible process”, Solid-State Electronics, vol. 53, no. 10, pp. 1092-1098, Oct, 2009. (Corresponding Author)

J23.   Huang CE, Chen YJ, Lai HC, King YC, Lin CJ*, “A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process”, IEEE Transactions on Electron Devices(TED), vol. 56, no. 6, pp. 1228-1234, Jun, 2009. (Corresponding Author)

J24.   Dai SH, Peng JJ, Chen CC, Lin CJ*, King YC, “Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal-Oxide-Semiconductor Process”, Japanese Journal of Applied Physics(JJAP), vol. 48, no. 4, Apr, 2009. (Corresponding Author) 

J25.   Chiang WJ, Lin CJ, King YC, Cho AT, Peng CT, Huang WM, “Integrated Ambient Light Sensor With Nanocrystalline Silicon on a Low-Temperature Polysilicon Display Panel”, IEEE Transactions on Electron Devices, vol. 56, no. 4, pp. 578-586, Apr, 2009.

J26.   Chiang WJ, Lin CJ, King YC, “Embedded Optical Sensor Using Gate-Body-Tied Thin-Film Transistor on Low-Temperature Poly-Silicon Display Panel”, Electrochemical and Solid State Letters, vol. 12, no. 5, pp. J51-J53, 2009. 

J27.   Chen CY, Huang CY, Lin CJ, King YC, “A low-temperature polycrystalline-silicon thin-film transistor micro-manipulation array with indium tin oxide micro-coils and real-time detection”, Journal of Micromechanics and Microengineering, vol. 19, no. 12, Dec, 2009. 

J28.   Shih HS, Fang SW, Kang AC, King YC, Lin CJ*, “High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory”, Applied Physics Letters(APL), vol. 93, no. 21, Nov, 2008. (Corresponding Author)

J29.   Lee TY, Chiu CC, Liu YC, Liu CC, King YC, Lin CJ*, “A new embedded one-time-programmable MNOS memory fully compatible to LTPS fabrication for system-on-panel (SOP) applications”, IEEE Electron Device Letters(EDL), vol. 29, no. 8, pp. 906-908, Aug, 2008. (Corresponding Author)

J30.   Lai HC, Huang CE, King YC, Lin CJ*, “Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal-Oxide-Semiconductor Logic Technology”, Japanese Journal of Applied Physics(JJAP), vol. 47, no. 11, pp. 8369-8374, Nov, 2008. (Corresponding Author)

J31.   Chen YJ, Huang CE, Chen HM, Lai HC, Shih JR, Wu K, King YC, Lin CJ*, “A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology”, IEEE Electron Device Letters (EDL), vol. 29, no. 8, pp. 938-940, Aug, 2008. (Corresponding Author) 

Conference Paper

C1.  M.C. Hsieh, Y.C. Liao, Y.W. Chin, C.H. Lien, T.S. Chang, Y.D. Chih, S. Natarajan, M.J. Tsai, Y.C. King, and C.J. Lin, "Ultra High Density 3D Via RRAM in Pure 28nm CMOS Process", International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 2013. (Corresponding Author)

C2.  C.H. Wang, K.Y. Dai, K.H. Shen, Y.H. Wang, and M.J. Tsai, C.J. Lin and Y.C. King, “Magnetic Wireless Interlayer Transmission through Perpendicular MTJ for 3D-IC Applications,” International Electron Devices Meeting (IEDM), Washington, D.C., Dec. 2013.

C3.     W. C Shen, C. Y. Mei , Y. D. Chih, S. S Sheu, M. J. Tsai, Y. C. King, C. J. Lin, “High-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process,” 2012 International Electron Devices Meeting (IEDM), San Francisco, Dec. 2012. (Corresponding Author)

C4.     J. M. Wang, K. Y. Tai1, L. C. Wang, C. Lin, C. H. Huang, C. J. Lin, and Y. C. King, “Super Junction Power MOSFET by Multi-step Trench Process,” 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012

C5.     T. H. Yang, U. Liauh, Y. D. Chih, C. J. Lin, Y. C. King, “Single Contact RRAM in Pure 65nm CMOS Logic Process,” 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012 (Corresponding Author)

C6.     Chang MF, Wu CW, Kuo CC, Shen SJ, Yang SM, Lin KF, King YC, Lin CJ, and Chih YD, “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time” 2012 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012.  

C7.     Chang MF, Shen SJ, Liu CC, Wu CW, Lin YF, Wu SC, Huang CE, Lai HC, King YC, Lin CJ, Liao HJ, Chin YD, Hiroyuki Yamacuchi, “An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory”, 2011 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2011. 

C8.     Wang CH, Tsai YH, Lin KC, Chang M. F., King Y. C., Lin CJ*, Sheu, S. S., Chen, Y. S., Lee, H. Y., Chen, F. T., Tsai, M. J., “Three-Dimensional 4F(2) ReRAM Cell with CMOS Logic Compatible Process”, 2010 International Electron Devices Meeting (IEDM), Dec. 2010. (Corresponding Author)

C9.     Tseng YH, Shen WC, Huang CE, Lin CJ*, King YC, “Electron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis”, 2010 International Electron Devices Meeting (IEDM), Dec. 2010. (Corresponding Author)

C10. Lee TY, Chiu CC, Lin CJ, King, Y. C., Chang, M. L., Tseng, C. C., Liu, P. L., Liu, C. C., “High-Uniformity 2T1C AMOLED Panels by Using a New Built-In Trimming Method”, 2009 International Symp. of the Society for Information Display (SID). 

C11. Tseng YH, Huang CE, Kuo CH, Chih YD, Lin CJ*, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, 2009 IEEE International Electron Devices Meeting (IEDM), Dec. 2009. (Corresponding Author)

Granted Patent (2008 - 2013)

US Patent

US1.    U.S. Patent, No.8184486, 2012, “Tunable current driver and operating method thereof”, by Lin; Chrong-Jung, King; Ya-Chin

US2.    U.S. Patent, No.8232978, 2012, “Optical reflected touch panel and pixels and system thereof”, by Chiang; Wen-Jen, Cho; An-Thung, Lin; Chrong-Jung, Peng; Chia-Tien, King; Ya-Chin, Lin; Kun-Chih, Chao; Chih-Wei, Weng; Chien-Sen, Gan; Feng-Yuan

US3.    U.S. Patent, No.8143090, 2012, “Method of fabricating photo sensor”, by Weng; Chien-Sen, Chao; Chih-Wei, Lin; Chrong-Jung, King; Ya-Chin

US4.    U.S. Patent, No. 8107274, 2012, “Variable and reversible resistive element, non-volatile memory device and methods for operating and manufacturing the non-volatile memory device”, by  Lin; Chrong-Jung, King; Ya-Chin

US5.    U.S. Patent, No. 8093649, 2012, “Flash memory cell”, by Lin; Chrong-Jung, King; Ya-Chin

US6.    U.S. Patent, No.7952159, 2011, “Photo sensor and flat display panel”, by Weng; Chien-Sen, Chao; Chih-Wei, Lin; Chrong-Jung, King; Ya-Chin

US7.    U.S. Patent, No.7903444, 2011, “One-time programmable memory and operating method thereof”, by Lin; Chrong-Jung , King; Ya-Chin

US8.    U.S. Patent, No. 7829920, 2010, “Photo Detector and a Display Panel having the Same ”, by Cho; An-Thung, Peng; Chia-Tien, Lin; Kun-Chih, Chiang; Wen-Jen, Chen; Chih-Yang, Lin; Chrong-Jung, King; Ya-Chin, Chao; Chih-Wei, Weng; Chien-Sen, Gan; Feng-Yuan

US9.    U.S. Patent, No. 7551494, 2009, “SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD ”, by Lin; Chrong-Jung, Chen; Hsin-Ming, Shen; Shih-Jye, King; Ya-Chin, Hsu; Ching-Hsiang

US10.        U.S. Patent, No. 7575948, 2009, “Method for operating photosensitive device ”, by Lin; Chrong-Jung, King; Ya-Chin

 

Taiwan Patent

TW1.      ROC Patent, No. I363425, 2012, “一種半導體記憶元件、一種可調式電流驅動裝置及其操作方法” by 林崇榮,金雅琴

TW2.      R ROC Patent, No. I353672, 2011, “非揮發性記憶體及其製造方法”, by 林崇榮, 陳信銘, 金雅琴

TW3.      ROC Patent, No. I344026, 2011, “光感測器以及具有此光感測器之顯示面板”, by卓恩宗, 彭佳添, 林昆志, 江文任, 陳至揚, 林崇榮, 金雅琴, 趙志偉, 翁健森, 甘豐源

TW4.      ROC Patent, No. I324832, 2010, “光感測元件及其製作方法”,翁健森, 趙志偉, 林崇榮, 金雅琴

TW5.      ROC Patent, No. I333691, 2010, “雙閘極非揮發型記憶胞及其操作方法”, by 金雅琴, 林崇榮, 陳信銘

TW6.      ROC Patent, No. I312190, 2009, “奈米矽顆粒型架構之影像感測元件”, by 金雅琴, 林崇榮

TW7.      ROC Patent, No. I292622, 2008, “單層晶矽非揮發性記憶體的操作方法”, by林崇榮, 陳信銘,沈士傑, 金雅琴, and徐清祥

TW8.      ROC Patent, No. I299866, 2008, “單層晶矽非揮發性記憶體的操作方法”, by林崇榮, 陳信銘, 沈士傑, 金雅琴, 徐清祥

TW9.      ROC Patent, No. I294692, 2008, “無閘極非揮發型記憶胞及其操作方法”, by金雅琴, 林崇榮

TW10.  ROC Patent, No. I295848, 2008, “非揮發性U型閘極側壁雙位元記憶體及其操作方法”, by金雅琴, 林崇榮

TW11.  ROC Patent, No. I298933, 2008, “閘極側壁儲存之雙位元快閃記憶體及其操作方法”, by金雅琴, 林崇榮


 

 

 

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 http://www.eetimes.com/electronics-news/4397124/Taiwan-embeds-ReRAM-in-28-nm-logic-process

PUBLICATIONS (Before 2008)

Journal Papers (Before 2008)

1. "Enhanced Tunneling Characteristics of PECVD Silicon-Rich-Oxide (SRO) for the Application in Low Voltage Flash EEPROM,“ IEEE Trans. on Electron Device (ED), pp.2021-2023, Nov., Vol. 43, 1996.

2. “A New Ultra Low Voltage SRO NAND Cell, Jpn. J. Appl. Phys. (JJAP), pp.1030 – 1034, Vol. 36, 1997.

3. “Quantum Size Effects on Photoluminescence from Si Nanocrystals in PECVD Silicon-Rich-Oxide, Applied Surface Science, pp.116-120, 1997.

4. “Performance and Reliability Trade-off of Large-Title-Angle Implant P-Pocket (LAP) on Stacked Gate Memory Device, Jpn. J. Appl. Phys. (JJAP), pp.4289 – 4294, Vol.36, 1997.

5. “Degradation of Flash Memory Using Drain Avalanche Hot Electron (DAHE) self Convergence Operation Scheme, Jpn. J. Appl. Phys. (JJAP), pp.778-780, Vol.37, 1998.

6. “High Speed F-N Operated Volatile Memory Cell With Stacked PECVD Nanocrystalline Si Layer Structure, Jpn. J. Appl. Phys. (JJAP), pp.1517-1519, Vol.37, 1998.

7. ” A flash-based SOC technology using a split-gate cell,” Microelectronic Engineering, Volume 59 (1-4): 203-211 Nov, 2001

8. ”An Analytical Programming Model for the Drain Coupling Source Side Injection Split Gate Flash EEPROM,” IEEE Trans. on Electron Device (ED), Volume 52, Issue 3, pp.385-391, 2005.

9. ”On the dynamic coupling split gate Flash using quasi-two dimensional analysis,” Circuit, Device and Systems, IEE Proceedings, Oct. 2005.

10.”On the Application of Analytical Model for Drain-coupling Split Gate Flash: An Analytical Solution to Source-Side Injection Multilevel Programming,” Jpn. J. Appl. Phys. (JJAP), Vol.45, No. 03, pp.1517-1519, 2006.

11.”On the Application of Analytical Model for Drain-coupling Split Gate Flash: An Analytical Solution to Source-Side Injection Multilevel Programming,” IEEE ELECTRON DEVICE LETTERS (EDL), VOL. 28, NO. 9, SEPTEMBER 2007, pp.837-839. :2.716

12.”A 0.26-μm2 U-Shaped Nitride-Based Programming Cell on Pure 90-nm CMOS Technology,” IEEE ELECTRON DEVICE LETTERS (EDL), VOL. 28, NO. 9, SEPTEMBER 2007, pp.837-839. :2.716

13.”Stress-induced width-dependent degradation of low-temperature polycrystalline silicon thin-film transistor,” APPLIED PHYSICS LETTERS (APL), 90, 183502, APRIL, 2007. :3.977

14.,” Embedded TFT NAND-Type Nonvolatile Memory in Panel,” IEEE ELECTRON DEVICE LETTERS (EDL), VOL. 28, NO. 6, JUNE 2007, pp.499-501. :2.716

15.”Silicon nanocrystal-based photosensor on low-temperature polycrystalline-silicon panels,” APPLIED PHYSICS LETTERS (APL), 91, 051120, AUGUST, 2007. :3.977

16.”Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor,” IEEE ELECTRON DEVICE LETTERS (EDL), VOL. 28, NO. 6, JUNE 2007. :2.716

17. “P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance” Jpn. J. Appl. Phys. (JJAP), Vol.46, No. 7A, pp.4046-4049, 2007. :1.222

18. “Trench termination design and analysis in low-voltage N-channel trench power metal-oxide-semiconductor field-effect transistor”, Japanese Journal of Applied Physics(JJAP), vol. 47, no. 3, pp. 1507-1511, Mar, 2008. (Corresponding Author)

19. “Leakage suppression of low-voltage transient voltage suppressor”, IEEE Transactions on Electron Devices(TED), vol. 55, no. 1, pp. 206-210, Jan, 2008. (Impact factor in top of 10)

20 “Silicon-nanocrystal-based photosensor integrated on low-temperature polysilicon panels”, Journal of the Society for Information Display(SID), vol. 16, no. 7, pp. 777-786, Jul, 2008.

21. “A new antifuse cell with programmable contact for advance CMOS logic circuits”, IEEE Electron Device Letters(EDL), vol. 29, no. 5, pp. 522-524, May, 2008. (Impact factor in top of 8) (Corresponding Author)

 

Conference Papers (Before 2008)

1.          “Mobility Degradation Induced by Substrate-Hot-Electron Generated Interface Traps at Different Stress Voltages and Temperatures,” The International Conference on Solid State Devices and Materials (SSDM), 1993.    

2.          "Enhanced Tunneling Characteristics in Silicon-Rich-Oxide Films Deposited Using PECVD for Flash EEPROM,“ The 1994 International Conference on Electronic Materials (ICEM'94).

3.          "Enhanced Tunneling Characteristics in Silicon-Rich-Oxide Films Deposited Using PECVD for Flash EEPROM Application,“ Seventh International Conference on Solid Films and Surfaces (ICSFS-7), 1994.

4.          "High Tunneling Efficiency of PECVD Silicon Rich Oxide (SRO) for the Application in Low Voltage Flash EEPROM,“ SEMI Taiwan IC Technical Conference, 1995.

5.          "Process Optimization for Preventing Boron-Penetration Using P or As Co-Implant in P-Poly gate of P-MOSFETs,“ VLSI Tech., Systems, and Application (VLSI-TSA), 1995.

6.          “Quantum Size Effects on Photoluminescence from Si Nanocrystals in PECVD Silicon-Rich-Oxide,” Eighth International Conference on Solid Films and Surfaces (ICSFS-8), 1996.

7.          Ultra Fast Write Speed, Long Refesh Time, Low Power F-N Operated Volatile Memory Cell with Stacked Nanocrystalline Si Film,” IEEE International Electron Device Meeting (IEDM), P515 – P518, 1996.

8.      “The Application of Large-Title-Angle Implant P-Pocket (LAP) on Stacked Gate Memory Device,” Int’l EDMS., 1997.

9.      “Gate and Read Disturb Failure Mechanisms in Source-Side Erased Flash EEPROM Memory Cell,” Int’l EDMS, 1998.

10.   "The Dominant Mechanisms of Hot-Hole Injection Induced SILC and Their Correlation with Disturb in N-Flash Memory Cells,“ IEEE VLSI Tech., Systems, and Application, (VLSI-TSA), 1999.

11.   "A Novel High Performance and Reliability P-Type Floating Gate N-Channel Flash EEPROM,“, IEEE Symposium on VLSI Techhnology (VLSI), 3A-2, 1999.

12.   "A Novel ONO of Nitridized Bottom Oxide for High Density Stack Gate Flash Memory,“The International Conference on Solid State Devices and Materials (SSDM), 1999.

13.   "N-Channel Versus P-Channel Flash EEPROM – Which one has better reliabilities,“ IEEE 39th International Reliability Physics Symposium (IRPS), pp.67-72, 2001.

14.   “A New CMOS Logic Anti-Fuse Cell with Programmable Contact,” IEEE 22nd IEEE Nonvolatile Semiconductor Memory Workshop (NVSMW), 2007, pp.48 – 51.

15.   "Degradation Dependent on Channel Width in Sequential Lateral Solidified Poly-Si Thin Film Transistors,“IEEE 45th Annual International Reliability Physics Symposium (IRPS), 2007, p. 682 – p.683.

16.   “Silicon Nanocrystals Photo Sensor Integrated on Low-Temperature Polycrystalline-Silicon Panels,” 2007 International Society for Display Information (SID), 2007, pp.294 – 297.

17.   “Integrated Ambient Light Sensor in LTPS LCD panel with Silicon nanocrystals photosensor,” The 14th International Display Workshops (IDW), 2007, pp.103 – 106.

18.   "Leakage Supression of Low Voltage Transient Voltage Suppressor,“ IEEE 45th Annual International Reliability Physics Symposium (IRPS), 2007, p. 592 – p.593.

19.   "Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor,“International Conference on Solid State Devices and Materials (SSDM), 2007.

20.   "High Sensitivity of Dielectric films Structure for Advanced CMOS Image Sensor Technology,“ IEEE International Image Sensor Workshop (IISW), 2007

21.   “A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process,” IEEE International Electron Device Meeting (IEDM), 2007, pp.91 – 94.

22.   “45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process,” IEEE International Electron Device Meeting (IEDM), 2007, pp.95 – 98.

23.   “Low voltage transient voltage suppressor with v-groove structurec”, 2008 IEEE International Reliability Physics Symposium Proceedings (IRPS), Apr. 2008.

 

US Patent (Before 2008)

1. U.S. Patent No.5861634, 1999, “Charge Collection Structure Detecting Radiation Induced Charges During Integrated Circuit Processing”, by Ching-Hsiang Hsu, Chrong Jung Lin, and Mong Song Liang

2. U.S. Patent No.6013551, 2000, “Self-Aligned Floating Gate Flash Memory Cell”, by Jong Chen, and Chrong Jung Lin 

3. U.S. Patent No.5960284, 1999, “Vertical Channel Flash Memory Cell Fabrication (1)”, by Chrong Jung Lin, Shui-Hung Chen, Jong Chen, and Di-Son Kuo

4. U.S. Patent No.6437397, 2002, “Vertical Channel Flash Memory Cell Fabrication (2)”, by Chrong Jung Lin, Shui-Hung Chen, Jong Chen, and Di-Son Kuo

5. U.S. Patent No.6011288, 2000, “Vertical Channel Flash Memory Cell Structure (1)”, by Chrong Jung Lin, Shui-Hung Chen, Jong Chen, and Di-Son Kuo

6. U.S. Patent No.6066874, 2000, “Vertical Channel Flash Memory Cell Structure (2)”, by Chrong Jung Lin, Shui-Hung Chen, Jong Chen, and Di-Son Kuo

7. U.S. Patent No.6127226, 2000, “Vertical Channel Flash Memory Cell Using P/N Junction Isolation”, by Chrong Jung Lin, Jong Chen, Shui-Hung Chen, and Di-Son, Kuo

8. U.S. Patent No.5970341, 1999, “Vertical Channel Split Gate Flash Memory Cell Structure”, by Chrong Jung Lin, Chia-Ta Hsieh, Jong Chen, and Di-Son Kuo

9. U.S. Patent No.6074915, 2000, “Embedded Flash Memory with Salicide and SAC Structure”, by Jong Chen, Chrong Jung Lin, Hung-Der Su, and Di-Son Kuo

10. U.S. Patent No.6037223, 2000, “The Novel Stack Gate Flash Memory with Symmetric SAC Structure”, by Hung-Der Su, Chrong Jung Lin, Jong Chen, and Di-Son Kuo

11. U.S. Patent No.6001687, 1999, “Using SiN Spacer as Hard Mask to Form Self-Aligned Source (SAS) in Flash Cell”, by Wen-Ting Chu, Di-Son Kuo, Chrong Jung Lin, Hung-Der Su, and Jong Chen

12. U.S. Patent No.6078076, 2000, “Vertical Channel Split Gate Flash Memory Cell Structure”, by Chrong Jung Lin, Chia-Ta Hsieh, Jong Chen, and Di-Son Kuo

13. U.S. Patent No.6133097, 2000, “A Method to Shrink Array Dimension by One Mask Defining of Cell and Source Line in Split Gate Flash (I)”, by Chia-Ta Hsieh, Chrong Jung Lin, Shui-Hung Chen, Di-Son Kuo

14. U.S. Patent No.6326662, 2001, “A Method to Shrink Array Dimension by One Mask Defining of Cell and Source Line in Split Gate Flash (II)”, by Chia-Ta Hsieh, Chrong Jung Lin, Shui-Hung Chen, and Di-Son Kuo

15. U.S. Patent No.6063664, 2000, “EEPROM with Trenched Structure”, by Jong Chen, Chrong Jung Lin, and Di-Son Kuo

16. U.S. Patent No.6242314, 2001, “Method of On-Chip Temperature Controller by Co-Implant Poly Resistor”, by Shui-Hung Chen, Chrong Jung Lin, and Jiaw-Ren Shih

17. U.S. Patent, No.6087222, 2000, “Vertical Split Gate Flash Memory (1)”, by Chrong Jung Lin, Shui-Hung Chen, and Di-Son Kuo

18. U.S. Patent, No.6391719, 2002, “Vertical Split Gate Flash Memory (2)”, by Chrong Jung Lin, Shui-Hung Chen and Di-Son Kuo

19. U.S. Patent, No.6583466, 2003, “Vertical Split Gate Flash Memory (3)”, by Chrong Jung Lin, Shui-Hung Chen and Di-Son Kuo

20. U.S. Patent, No.6093606, 2000, “Vertical Stacked gate Flash Memory (1)”, by Chrong Jung Lin, Shui-Hung Chen, and Mong-Song Liang

21. U.S. Patent, No.6548856, 2003, “Vertical Stacked gate Flash Memory (2)”, by Chrong Jung Lin, Shui-Hung Chen, and Mong-Song Liang

22. U.S. Patent, No.6127227, 2001, “Thin ONO Thickness Control and Gradual Gate Oxidation Suppression by N2 Treatment in Flash Memory”, by Chrong Jung Lin, Jong Chen, Hung-Der Su, and Di-Son Kuo

23. U.S. Patent, No.6190969, 2001, “Flash Memory Cell with CMP Planarizing Floating Gate”, by Chrong Jung Lin, Jong Chen, Hung-Dr Su, and Di-Son Kuo

24. U.S. Patent, No.6495880, 2002, “Flash Memory Cell with CMP Planarizing Floating Gate”, by Chrong Jung Lin, Jong Chen, Hung-Der Su, and Di-Son Kuo

25. U.S. Patent, No.6133096, 2001, “The Fabrication Stack Gate Flash Memory with Symmetric SAC Structure and Salicide Periphery”, by Hung-Der Su, Jong Chen, Chrong Jung Lin, and Di-Son Kuo

26. U.S. Patent, No.6153494, 2000, “A Method to Increase The Coupling Ratio of Word Line to Floating Gate by Lateral Coupling in Stacked Gate Flash”, by Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong Jung Lin, Jong Chen, and Hung-Der Su

27. U.S. Patent, No.6225162, 2001, “Step-Shaped Floating Poly-Si to Improve Gate Coupling Ratio for Flash Memory Application”, by Chrong Jung Lin and Shui-Hung Chen

28. U.S. Patent, No.6130168, 2000, “Using ONO as Hard Mask ro Reduce STI Oxide Loss of Low Voltage Device”, by Wen-Ting Chu, Di-Son Kuo, Chrong Jung Lin, Hung-Der Su, and Jong Chen

29. U.S. Patent, No.6251744, 2001, “The Novel Implant Method to Improve The Characteristic of The High Voltage Isolation and High Voltage Breakdown”, by Hung-Der Su, Chrong Jung Lin, Jong Chen, Wen-Ting Chu, Hung-Cheng Sung, and Di-Son Kuo

30. U.S. Patent, No.6372525, 2002, “A Quick Wafer-Level Detecting Pattern for Antenna Effect in VLSI Process (1)”, by Chrong Jung Lin and Hsin-Ming Chen

31. U.S. Patent, No.6586765, 2003, “A Quick Wafer-Level Detecting Pattern for Antenna Effect in VLSI Process (2)”, by Chrong Jung Lin and Hsin-Ming Chen

32. U.S. Patent, No.6297098, 2001, “Tilt-Angle Ion Implant to Improve Junction Breakdown in Flash Memory Application”, by Chrong Jung Lin, Hung-Der Su, Jong Chen, and Wen-Ting Chu

33. U.S. Patent, No.6348382, 2002, “The New Integration Process to Increase High Device Breakdown Voltage”, by Hung-Der Su, Chrong Jung Lin, Jong Chen, and Wen-Ting Chu

34. U.S. Patent, No.6207532, 2001, “New STI Process for Improving Isolation for Deep Sub-Micron Process”, by Chrong Jung Lin, Shui-Hung Chen, and Jiaw-Ren Shih

35. U.S. Patent, No.6277723, 2001, “A Novel Plasma Damage Protection Cell Using Floating N/P/N and P/N/P Structure (1)”, by Jiaw-Ren Shih, Shui-Hung Chen, Jian-Hsing Lee, and Chrong Jung Lin

36. U.S. Patent, No.6437408, 2002, “A Novel Plasma Damage Protection Cell Using Floating N/P/N and P/N/P Structure (2)”, by Jiaw-Ren Shih, Shui-Hung Shen, Jian-Hsing Lee, and Chrong Jung Lin 

37. U.S. Patent, No.6261905, 2001, “A Novel Flash Memory Structure with Stacking Gate by Using Damascene Structure”, by Jong Chen, Chrong-Jung Lin, Hung-Der Su, and Wen-Ting Chu

38. U.S. Patent, No.6124177, 2000, “An Advanced and Novel MOSFET Structure”, by Chrong Jung Lin, Hung Der Su, Jong Chen, and Wen-Ting Chu 

39. U.S. Patent, No.6108242, 2000, “An Enhanced Tunneling Tip for High Speed and Low Voltage Split Gate Flash Memory”, by Chrong Jung Lin and Hsin-Ming Chen

40. U.S. Patent, No.6576558, 2003, “A High Aspect Ratio Shallow Trench Oxide (STI) Using SIMOX (SOI)”, by Chrong Jung Lin and Hsin-Ming Chen 

41. U.S. Patent, No.6420233, 2002, “A Method to Improve Programming and Erasing Speed by Local Heavy Implant in Split gate Flash”, by Chia-Ta Hsieh, Di-Son Kuo, Jack Yeh, Chung-Li Chang, Wen-Ting Chu, and Chrong Jung Lin

42. U.S. Patent, No.6297099, 2001, “A Method to Free Control Tunneling Thickness on Poly Tip of Flash”, by Chia-Ta Hsieh, Di-Son Kuo, Jack Yeh, Chrong Jung Lin, Wen-Ting Chu, and Chung-Li Chang 

43. U.S. Patent, No.6465836, 2002, “Sharp Ring Tip Vertical Split Gate Flash Memory”, by Chrong Jung Lin, Sheng-Wei Tsao, Di-Son Kuo, Jack Yeh, Wen-Ting Chu, Chung-Li Chang and Chia-Ta Hsieh

44. U.S. Patent, No.6544828, 2003, “Adding A Poly-Strip on Isolation’s Edge to Improve Endurance of High Voltage NMOS on EEPROM”, by Wen-Ting Chu, Di-Son Kuo, Jack Yeh, Chia-Ta Hsieh, Chrong Jung Lin, and Cheng-Wei Tsaur

45. U.S. Patent, No.6624025, 2003, “A Method with Trench Source to Increase The Coupling of Source to Floating Gate in Split Gate Flash”, by Chia-Ta Hsieh, Di-Son Kuo, Chrong Jung Lin, Wen-Ting Chu

46. U.S. Patent, No.6172395, 2001, “Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby”, by Jong Chen and Chrong Jung Lin  

47. U.S. Patent, No.6724036, 2004, “Stacked gate flash memory cell with floating gate and increased coupling ratio”, by Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong Jung Lin, Jong Chen, and Hung-Der Su

48. U.S. Patent, No.6734055, 2004, “Multi-level (4 states/2 bits) stacked gate flash memory cell”, by Chrong Jung Lin, Shui-Hung Chen, and Hsin-Ming Chen

49. U.S. Patent, No.6787418, 2004, “Method of making the selection gate in a split gate flash eeprom cell and its structure”, by Wen-Ting Chu, Jack Yeh, and Chrong Jung Lin

50. U.S. Patent, No.6803625, 2004, “Method with trench source to increase the coupling of source to floating gate in split gate flash”, by Chia-Ta Hsieh, Di-Son Kuo, Chrong Jung Lin, and Wen-Ting Chu

51. U.S. Patent, No.6818936, 2004, “Scaled EEPROM cell by metal-insulator-metal (MIM) coupling”, by Chrong Jung Lin and Hsin Ming Chen

52. U.S. Patent, No.6838725, 2005, “Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application”, by Chrong Jung Lin and Shui-Hung Chen

53. U.S. Patent, No.66902978, 2005, “Method of making the selection gate in a split-gate flash EEPROM cell and its structure”, by Wen-Ting Chu, Jack Yeh, and Chrong Jung Lin

54. U.S. Patent, No.6933198, 2005, “Method for forming enhanced a real density split gate field effect transistor device array”, by Wen-Ting Chu, Chai-Ta Hsieh, and Chrong Jung Lin

55. U.S. Patent, No. 6982458, 2006, “Method of making the selection gate in a split-gate flash EEPROM cell and its structure”, by Wen-Ting Chu, Jack Yeh, and Chrong Jung Lin

 

ROC Patent (Before 2008)

1.     ROC Patent, No. 561533, 2002, “縮小浮動閘極間距之半導體製程”, by朱文定, 謝佳達, and林崇榮

2.     ROC Patent, No. 527652, 2002, "分閘式快閃記憶胞之選擇閘極的製作方法及其結構”, by朱文定, 葉壯格, and林崇榮

3.     ROC Patent, No. 525296, 2003, “使用CMP平坦化懸浮閘之快閃記憶體”, by林崇榮, 陳中, 蘇宏德, and郭迪生

4.     ROC Patent, No. 514913, 2002, “改善程式化及抹除速度之快閃記憶胞的製造方法”, by謝佳達, 郭迪生, 葉壯格, 張傳理, 朱文定, and林崇榮

5.     ROC Patent, No. 508671, 2002, “增加高電壓金氧半場效電晶體耐久性之方法”, by朱文定, 郭迪生, 葉壯格, 謝佳達, 林崇榮, and曹昇巍

6.     ROC Patent, No. 497219, 2002, “使用源極溝渠以增進源極與浮置閘極的耦合之分離閘極式快閃記憶體元件製作方法”, by謝佳達, 郭迪生, 林崇榮, and朱文定

7.     ROC Patent, No. 489484, 2002, “垂直型分離閘極式快閃記憶體及其製造方法”, by林崇榮, 曹昇巍, 郭迪生, 葉壯格, 朱文定, 張傳理, and謝佳達

8.     ROC Patent, No. 469603, 2001, “利用P/N接面隔離之快閃記憶體製程”, by林崇榮, 陳中, 陳遂泓, and郭迪生

9.     ROC Patent, No. 437074, 2001, “快閃記憶體之製作方法”, by林崇榮, 陳中, 蘇宏德, and郭迪生

10.   ROC Patent, No. 437015, 2001, “快閃記憶體之製程”, by林崇榮, 陳遂泓, 陳中, and郭迪生

11.   ROC Patent, No. 437014, 2001, “多重態之堆疊閘極快閃記憶體”, by林崇榮, 陳遂泓, and陳信銘

12.   ROC Patent, No. 434911, 2001, “高密度SOI垂直通道快閃記憶胞之形成方法”, by林崇榮 and陳信銘

13.   ROC Patent, No. 434910, 2001, “自我對準源汲極接觸快閃記憶體之製造方法及其結構”, by蘇宏德, 林崇榮, 陳中 and郭迪生

14.   ROC Patent, No. 430925, 2001, “增加高電壓元件崩潰電壓之離子佈植方法與結構”, by蘇宏德, 林崇榮, 陳中, 朱文定, 宋弘政, and郭迪生

15.   ROC Patent, No. 429623, 2001, “具金屬極板耦合電容之EEPROM結構”, by林崇榮 and陳信銘

16.   ROC Patent, No. 426936, 2001, “形成淺溝槽隔離區之方法”, by林崇榮, 陳遂泓, and施教仁

17.   ROC Patent, No. 424307, 2001, “嵌入式堆疊閘之快閃記憶體結構和製造方法”, by陳中, 林崇榮, 蘇宏德 and朱文定

18.   ROC Patent, No. 423155, 2001, “具步階狀懸浮閘極之高耦合率之快閃記憶體”, by林崇榮 and陳遂泓

19.   ROC Patent, No. 419784, 2001, “形成不同厚度之閘氧化層的方法”, by朱文定, 郭迪生, 林崇榮, 蘇宏德 and陳中

20.   ROC Patent, No. 419778, 2001, “快閃記憶體之自行對準源極製程”, by朱文定, 郭迪生, 林崇榮, 蘇宏德 and陳中

21.   ROC Patent, No. 418535, 2001, “具閘極側氣隙結構之金氧半場效電晶體”, by林崇榮, 蘇宏德, 陳中, and朱文定

22.   ROC Patent, No. 414972, 2001, “快速晶片層次之偵測天線效應”, by林崇榮 and陳信銘

23.   ROC Patent, No. 413889, 2001, “以雙載子接面電晶體避免天線效應之電晶體結構及其製造方法”, by施教仁, 陳遂泓, 林崇榮, and李建興

24.   ROC Patent, No. 412789, 2000, “提高半導體元件崩潰電壓之整合製程”, by蘇宏德, 林崇榮, 陳中 and朱文定

25.   ROC Patent, No. 411590, 2000, “分離式閘極之快閃記憶體”, by林崇榮 and陳信銘

26.   ROC Patent, No. 396420, 2000, “崁入式快閃記憶體之製程”, by陳中, 林崇榮, 蘇宏德, and郭迪生

27.   ROC Patent, No. 393746, 2000, “晶片上溫度控制器”, by陳遂泓, 林崇榮, and施教仁

28.   ROC Patent, No. 392346, 2000, “電性清除可程式唯讀記憶體之渠溝式浮置閘結構”, by陳中, 林崇榮, and郭迪生

29.   ROC Patent, No. 388131, 2000, “增加疊閘快閃記憶體元件字語線至懸浮閘極之耦合比之製造方法”, by 謝佳達, 郭迪生, 林雅芬, 林崇榮, 陳中, and蘇宏德

30.   ROC Patent, No. 386312, 2000, “垂直分閘快閃記憶體結構與方法”, by林崇榮, 陳遂泓, and郭迪生

31.   ROC Patent, No. 383468, 2000, “自我對準接觸源極和汲極製程的快閃記憶體製程”, by蘇宏德, 林崇榮, 陳中, and郭迪生

32.   ROC Patent, No. 373339, 1999, “垂宜疊閘快閃記憶體結構與方法”, by林崇榮, 陳遂泓, and梁孟松

33.   ROC Patent, No. 353219, 1999, “高密度之分離閘極快閃記憶體結構及其製造方法”, by謝佳達, 林崇榮, 郭迪生, and陳遂泓

34.   ROC Patent, No. 346685, 1998, “垂直式分離閘極之快閃記憶體結構”, by林崇榮, 謝佳達, 陳中, and郭迪生

35.   ROC Patent, No. 344879, 1998, “量測積體電路製程中因幅射所感應之電荷密度的方法”, by徐清祥, 梁孟松, and林崇榮

36.   ROC Patent, No. 337604, 1998, “自我對準懸浮閘之快閃記憶體結構及其製造方法”, by陳中 and林崇榮

37.   ROC Patent, No. 335538, 1998, “快閃記憶體”, by林崇榮, 陳遂泓, 陳中, and郭迪生

38.   ROC Patent, No. 260820, 1995, “以磷佈植防止硼穿透氧化層的製造方法”, by徐清祥, 陳遂泓, 林崇榮, 孫文堂, 洪允錠, and陳輝煌

39.   ROC Patent, No. 247971, 1995, “非對稱性快閃記憶單元及其製造方法”, by陳輝煌, 洪允錠, 許堯凱, 徐清祥, 林崇榮

40.   ROC Patent, No. 226480, 1994, “改良的互補式金氧半(CMOS)製程”, by洪允錠, 林崇榮, 陳遂泓, 孫文堂, 徐永珍, and徐清祥

41.  ROC Patent, No. I236733, 2005, “製作快閃記憶體元件之方法”, by 謝佳達, 郭迪生, 葉壯格 and林崇榮, 朱文定 and 張傳理